An energy efficient approximate multiplier for low power applications

Signal processing and multimedia are among the best applications for imprecise computing. The use of precise computation in arithmetic circuits can deliver more useful results without consuming electricity. Using recursive multiplication by approximate multipliers form compressors, we propose a new design that takes advantage partitions partial products. An compression 4:2 is used to three multiplier designs. Compared with previous designs, proposed demonstrated makes significant improvement accuracy as well power area reductions. compressor first two With reduced power, area, compared existing multipliers, Xilinx simulates synthesizes (1) simulation. software also simulate synthesize (2) high accuracy. (3) second compressor. In comparison designs (2), it consumes less area.